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? semiconductor components industries, llc, 2012 january, 2012 ? rev. 0 1 publication order number: ncp1253/d ncp1253 current-mode pwm controller for off-line power supplies the ncp1253 is a highly integrated pwm controller capable of delivering a rugged and high performance offline power supply in a tiny tsop ? 6 package. with a supply range up to 28 v, the controller hosts a jittered 65 khz or 100 khz switching circuitry operated in peak current mode control. when the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 khz. as the power further goes down, the part enters skip cycle while limiting the peak current. to avoid sub harmonic oscillations in ccm operation, adjustable slope compensation is available via the series inclusion of a simple resistor in the current sense signal. besides the auto ? recovery timer ? based short ? circuit protection, an over voltage protection on the v cc pin protects the whole circuitry in case of optocoupler destruction or adverse open loop operation. features ? fixed ? frequency 65 khz or 100 khz current ? mode control operation ? frequency foldback down to 26 khz and skip ? cycle in light load conditions ? adjustable ramp compensation ? internally fixed 4 ms soft ? start ? timer ? based auto ? recovery or latched short ? circuit protection ? frequency jittering in normal and frequency foldback modes ? latched ovp on v cc ? up to 28 v v cc operation ? extremely low no ? load standby power ? these are pb ? free devices typical applications ? ac ? dc converters for tvs, set ? top boxes and printers ? offline adapters for notebooks and netbooks pin connections 1 3 cs gnd 2 nc 4 drv 6 (top view) 5 v cc tsop ? 6 case 318g style 13 marking diagram fb http://onsemi.com (note: microdot may be in either location) 1 53xayw 1 53 = specific device code x = a, 2, c, or d a = assembly location y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on p age 2 of this data sheet. ordering information
ncp1253 http://onsemi.com 2 1 2 3 6 4 5 ncp1253 vbulk . . ramp comp. vout . figure 1. typical application schematic pin function description pin no. pin name function description 1 gnd ? the controller ground. 2 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 3 nc non ? connected pin the pin is electrically inert and can be grounded if necessary 4 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a means to introduce slope compensation. 5 v cc supplies the controller ? protects the ic this pin is connected to an external auxiliary voltage. an ovp comparator monitors this pin and offers a means to latch the converter in fault conditions. 6 drv driver output the driver?s output to an external mosfet gate. options controller frequency ocp latched ocp auto ? recovery NCP1253ASN65T1G 65 khz yes no ncp1253bsn65t1g 65 khz no yes ncp1253asn100t1g 100 khz yes no ncp1253bsn100t1g 100 khz no yes ordering information device package marking ocp protection switching frequency (khz) package shipping ? NCP1253ASN65T1G 53a latch 65 tsop ? 6 (pb ? free) 3000 / tape & reel ncp1253bsn65t1g 532 auto recovery 65 ncp1253asn100t1g 53c latch 100 ncp1253bsn100t1g 53d auto recovery 100 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1253 http://onsemi.com 3 s r q q 65 khz 100 khz clock vdd frequency modulation vcc drv vcc logic management and fault timer vdd power on reset rramp leb vdd rfb / 4.2 ipflag 4 ms ss ipflag gnd cs fb frequency foldback vskip the soft ? start is activated during: ? the startup sequence ? the auto ? recovery burst mode vlimit vfold clamp 20us time constant vovp vfb < 1.05 v ? setpoint = 250 mv 250 mv peak current freeze uvlo bo power on reset s r q q rlim figure 2. internal circuit architecture
ncp1253 http://onsemi.com 4 maximum ratings table symbol rating value unit v cc power supply voltage, v cc pin, continuous voltage 28 v maximum voltage on low power pins cs, and fb ? 0.3 to 10 v r j ? a thermal resistance junction ? to ? air 360 c/w t j,max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, human body model, all pins 2 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 200 v. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit vcc on v cc increasing level at which driving pulses are authorized 5 16 18 20 v vcc (min) v cc decreasing level at which driving pulses are stopped 5 8.2 8.8 9.4 v vcc hyst hysteresis vcc on ? vcc (min) 5 6 ? ? v v zener clamped v cc when latched off @ i cc = 500 a 5 ? 7 ? v icc1 start ? up current 5 ? ? 15 a icc2 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 0 5 ? 1.4 2.2 ma icc3 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 1 nf 5 ? 2.1 3.0 ma icc2 internal ic consumption with i fb = 50 a, f sw = 100 khz and c l = 0 5 ? 1.7 2.5 ma icc3 internal ic consumption with i fb = 50 a, f sw = 100 khz and c l = 1 nf 5 ? 3.1 4.0 ma iccstby internal ic consumption while in skip mode (v cc = 12 v, driving a typical 6 a/600 v mosfet) 5 550 a icc latch current flowing into v cc pin that keeps the controller latched ? t j = 0 to 125 c 5 32 a icc latch current flowing into v cc pin that keeps the controller latched ? t j = ? 40 c to 125 c 5 40 a drive output t r output voltage rise ? time @ c l = 1 nf, 10 ? 90% of output signal 6 ? 40 ? ns t f output voltage fall ? time @ c l = 1 nf, 10 ? 90% of output signal 6 ? 30 ? ns r oh source resistance 6 ? 13 ? r ol sink resistance 6 ? 6 ? i source peak source current, v gs = 0 v (note 3) 6 300 ma i sink peak sink current, v gs = 12 v (note 3) 6 500 ma v drvlow drv pin level at v cc close to vcc (min) with a 33 k resistor to gnd 6 8 ? ? v v drvhigh drv pin level at v cc = 28 v ? drv unloaded 6 10 12 14 v 3. guaranteed by design current comparator i ib input bias current @ 0.8 v input level on pin 4 4 0.02 a v limit1 maximum internal current setpoint ? t j = 25 c 4 0.744 0.8 0.856 v v limit2 maximum internal current setpoint ? t j = ? 40 to 125 c 4 0.72 0.8 0.88 v
ncp1253 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating current comparator v fold default internal voltage set point for frequency foldback trip point ? 45% of v limit 4 357 mv v freeze internal peak current setpoint freeze ( 31% of v limit ) 4 250 mv t del propagation delay from current detection to gate off ? state 4 100 150 ns t leb leading edge blanking duration 4 300 ns tss internal soft ? start duration activated upon startup, auto ? recovery ? 4 ms internal oscillator f osc oscillation frequency (65 khz version) ? 61 65 71 khz f osc oscillation frequency (100 khz version) ? 92 100 108 khz d max maximum duty ? ratio ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? 5 % f swing swing frequency ? 240 hz feedback section r up internal pull ? up resistor 2 20 k r eq equivalent ac resistor from fb to gnd 2 16 k i ratio pin 2 to current setpoint division ratio ? 4.2 v freeze (fb) feedback voltage below which the peak current is frozen 2 1.05 v frequency foldback v fold frequency foldback level on the feedback pin ? 45% of maximum peak current ? 1.5 v f trans transition frequency below which skip ? cycle occurs ? 22 26 30 khz v fold,end end of frequency foldback feedback level, f sw = f min 350 mv v skip skip ? cycle level voltage on the feedback pin ? 300 mv skip hysteresis hysteresis on the skip comparator ? 30 mv internal slope compensation v ramp internal ramp level @ 25 c (note 4) 4 2.5 v r ramp internal ramp resistance to cs pin 4 20 k 4. a 1 m resistor is connected from pin 4 to the ground for the measurement. protections v ovp latched overvoltage protection on the v cc rail 5 24 25.5 27 v t ovpdel delay before ovp confirmation on the v cc rail 5 20 s timer internal auto ? recovery fault timer duration ? 100 130 160 ms
ncp1253 http://onsemi.com 6 typical characteristics figure 3. d max vs. junction temperature figure 4. f osc vs. junction temperature figure 5. f trans vs. junction temperature figure 6. icc1 vs. junction temperature 100 khz 65 khz 100 khz 65 khz figure 7. icc2 vs. junction temperature figure 8. icc3 vs. junction temperature 100 khz 65 khz
ncp1253 http://onsemi.com 7 typical characteristics figure 9. v limit vs. junction temperature figure 10. v cc(on) vs. junction temperature figure 11. v cc(min) vs. junction temperature figure 12. v cc(hyst) vs. junction temperature figure 13. i cclatch vs. junction temperature figure 14. t leb vs. junction temperature
ncp1253 http://onsemi.com 8 typical characteristics figure 15. t del vs. junction temperature figure 16. t ss vs. junction temperature figure 17. v fold vs. junction temperature figure 18. v fold(fb) vs. junction temperature figure 19. v fold_end vs. junction temperature figure 20. v skip vs. junction temperature
ncp1253 http://onsemi.com 9 figure 21. v freeze vs. junction temperature figure 22. v freeze(fb) vs. junction temperature figure 23. timer vs. junction temperature figure 24. v ovp vs. junction temperature
ncp1253 http://onsemi.com 10 application information introduction the ncp1253 implements a standard current mode architecture where the switch ? off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part ? count and cost effectiveness are the key parameters, particularly in low ? cost ac ? dc adapters, open ? frame power supplies etc. capitalizing on the ncp1200 series success, the ncp1253 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a v cc ovp or an adjustable slope compensation signal. ? current ? mode operation with internal ramp compensation: implementing peak current mode control at a fixed 65 khz or 100 khz frequency, the ncp1253 offers an internal ramp compensation signal that can easily by summed up to the sensed current. sub harmonic oscillations can thus be compensated via the inclusion of a simple resistor in series with the current ? sense information. ? low startup current: reaching a low no ? load standby power always represents a difficult exercise when the controller draws a significant amount of current during start ? up. thanks to its proprietary architecture, the ncp1253 is guaranteed to draw less than 15 a maximum, easing the design of low standby power adapters. ? emi jittering: an internal low ? frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). ? frequency foldback capability: a continuous flow of pulses is not compatible with no ? load/light ? load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 v, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. when the feedback pin reaches 1.05 v, the peak current setpoint is internally frozen and the frequency continues to decrease. it can go down to 26 khz (typical) reached for a feedback level of 350 mv roughly. at this point, if the power continues to drop, the controller enters classical skip ? cycle mode. ? internal soft ? start: a soft ? start precludes the main power switch from being stressed upon start ? up. in this controller, the soft ? start is internally fixed to 4 ms. soft ? start is activated when a new startup sequence occurs or during an auto ? recovery hiccup. ? latched ovp on v cc : it is sometimes interesting to implement a circuit protection by sensing the v cc level. this is what ncp1253 does by monitoring its v cc pin. when the voltage on this pin exceeds 25.5 v typical, the pulses are immediately stopped and the part latches off. when the user cycles the v cc down or the converter recovers from a brown ? out event, the circuit is reset and the part enters a new start ? up sequence. ? short ? circuit protection: short ? circuit and especially over ? load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8 v maximum peak current limit is activated, an error flag is asserted and a time period starts, thanks to an internal timer. when the fault is validated, all pulses are stopped and the controller enters an auto ? recovery burst mode, with a soft ? start sequence at the beginning of each cycle. as soon as the fault disappears, the smps resumes operation. please note that some version offers an auto ? recovery mode as we just described, some do not and latch off in case of a short circuit. start ? up sequence the ncp1253 start ? up voltage is made purposely high to permit large energy storage in a small v cc capacitor value. this helps to operate with a small start ? up current which, together with a small v cc capacitor, will not hamper the start ? up time. to further reduce the standby power, the start ? up current of the controller is extremely low, below 15 a. the start ? up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage if you wish to save a few more mw.
ncp1253 http://onsemi.com 11 r1 200k r2 100k r3 100k c1 4.7uf d1 1n4007 d2 1n4007 d3 1n4007 d4 1n4007 cbulk 22uf input mains d5 1n4935 c3 47uf d6 1n4148 vcc aux. figure 25. the startup resistor can be connected to the input mains for further power dissipation reduction the first step starts with the calculation of the needed v cc capacitor which will supply the controller until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 and 20 ms. considering that we need at least an energy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: cv cc i cc t 1 vcc on vcc min 3m 10m 9 3.3 f (eq. 1) let us select a 4.7 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t 1 . the v cc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 to the vcc on of the ic, 18 v typical. this current has to be selected to ensure a start ? up at the lowest mains (85 v rms) to be less than 3 s (2.5 s for design margin): i charge vcc on c vcc 2.5 18 4.7 2.5 34 a (eq. 2) if we account for the 15 a that will flow inside the controller, then the total charging current delivered by the start ? up resistor must be 49 a. if we connect the start ? up network to the mains (half ? wave connection then), we know that the average current flowing into this start ? up resistor will be the smallest when v cc reaches the vcc on of the controller: if we account for the 15 a that will flow inside the controller, then the total charging current delivered by the start ? up resistor must be 49 a. if we connect the start ? up network to the mains (half ? wave connection then), we know that the average current flowing into this start ? up resistor will be the smallest when v cc reaches the vcc on of the controller: i cvcc,min v ac,rms 2 vcc on r start ? up (eq. 3) to make sure this current is always greater than 49 a, the maximum value for r start ? up can be extracted: r start ? up v ac,rms 2 vcc on i cvcc,min 85 1.414 18 49 413 k (eq. 4) this calculation is purely theoretical, considering a constant charging current. in reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the v cc capacitor. this brings a decrease in the charging current and an increase of the start ? up resistor, for the benefit of standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter. if we chose the 400k resistor as suggested by equation 4, the dissipated power at high line amounts to: p rstart,max v ac,peak 2 4r start ? up 320 2 2 4 400k 105k 1.6meg 66 mw (eq. 5) now that the first v cc capacitor has been selected, we must ensure that the self ? supply does not disappear when in no ? load conditions. in this mode, the skip ? cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the v cc capacitor. if this ripple is too large, chances exist to touch the vcc min and reset the controller into a new start ? up sequence. a solution is to grow this capacitor but it will obviously be detrimental to the start ? up time. the option offered in figure 25 elegantly
ncp1253 http://onsemi.com 12 solves this potential issue by adding an extra capacitor on the auxiliary winding. however, this component is separated from the v cc pin via a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self ? supply of the controller without jeopardizing the start ? up time and standby power. triggering the scr the latched ? state of the ncp1253 is maintained via an internal thyristor (scr). when the voltage on the v cc pin exceeds the internal latch voltage, the scr is fired and immediately stops the output pulses. when this happens, all pulses are stopped and v cc is discharged to a fix level of 7 v typically: the circuit is latched and the converter no longer delivers pulses. to maintain the latched ? state, a permanent current must be injected in the part. if too low of a current, the part de ? latches and the converter resumes operation. this current is characterized to 32 a as a minimum but we recommend including a design margin and select a value around 60 a. the test is to latch the part and reduce the input voltage until it de ? latches. if you de ? latch at v in = 70 vrms for a minimum voltage of 85 vrms, you are fine. if it precociously recovers, you will have to increase the start ? up current, unfortunately to the detriment of standby power. the most sensitive configuration is actually that of the half ? wave connection proposed in figure 25. as the current disappears 5 ms for a 10 ms period (50 hz input source), the latch can potentially open at low line. if you really reduce the start ? up current for a low standby power design, you must ensure enough current in the scr in case of a faulty event. an alternate connection to the above is shown below (figure 26): l1 n vcc 1 meg 1 meg figure 26. the full ? wave connection ensures latch current continuity as well as a x2 ? discharge path. in this case, the current is no longer made of 5 ms ?holes? and the part can be maintained at a low input voltage. experiments show that these 2 m resistor help to maintain the latch down to less than 50 vrms, giving an excellent design margin. standby power with this approach was also improved compared to figure 25 solution. please note that these resistors also ensure the discharge of the x2 ? capacitor up to a 0.47 f type. the de ? latch of the scr occurs when the injected current in the v cc pin falls below the minimum stated in the data ? sheet (32 a at room temp). frequency foldback the reduction of no ? load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed ? frequency type of operation. this controller implements a switching frequency foldback when the feedback voltage passes below a certain level, v fold , set around 1.5 v. at this point, the oscillator enters frequency foldback and reduces its switching frequency. the peak current setpoint is following the feedback pin until its level reaches 1.05 v. below this value, the peak current freezes to v fold /4.2 (250 mv or 31% of the maximum 0.8 ? v setpoint) and the only way to further reduce the transmitted power is to diminish the operating frequency down to 26 khz. this value is reached at a feedback voltage level of 350 mv typically. below this point, if the output power continues to decrease, the part enters skip cycle for the best noise ? free performance in no ? load conditions. depicts the adopted scheme for the part.
ncp1253 http://onsemi.com 13 f sw v fb v cs v fb 65 khz 26 khz 350 mv v fold 3.4 v v fold 3.4 v 0.8 v
0.36 v fb v freeze
0.25 v 1.05 v 1.5 v 1.5 v max min max min v fold,end frequency peak current setpoint f sw v fb v cs v fb 65 khz 26 khz 350 mv v fold 3.4 v v fold 3.4 v 0.8 v
0.36 v fb v freeze
0.25 v 1.05 v 1.5 v 1.5 v max min max min v fold,end frequency peak current setpoint figure 27. by observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load auto ? recovery short ? circuit protection in case of output short ? circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than 100 ms, the driving pulses are stopped and v cc falls down as the auxiliary pulses are missing. when it crosses vcc (min) , the controller consumption is down to a few a and the v cc slowly builds up again thanks to the resistive starting network. when v cc reaches vcc on , the controller attempts to re ? start, checking for the absence of the fault. if the fault is still there, the supply enters another cycle of so ? called hiccup. if the fault has disappeared, the power supply resumes operations. please note that the soft ? start is activated during each of the re ? start sequence. 1 vcc 2 vdrv 3 ilprim 500u 1.50m 2.50m 3.50m 4.50m time in seconds 445m 1.41 2.38 3.35 4.32 ilprim in amperes ? 8.13 ? 2.12 3.89 9.90 15.9 vcc in volts ? 11.5 ? 2.72 6.05 14.8 23.6 vdrv in volts plot1 2 1 3 () cc vt () drv vt () p l it ss 1 vcc 2 vdrv 3 ilprim 500u 1.50m 2.50m 3.50m 4.50m time in seconds 445m 1.41 2.38 3.35 4.32 ilprim in amperes ? 8.13 ? 2.12 3.89 9.90 15.9 vcc in volts ? 11.5 ? 2.72 6.05 14.8 23.6 vdrv in volts plot1 2 1 3 () cc vt () drv vt () p l it ss figure 28. an auto ? recovery hiccup mode is entered in case a faulty event longer than 100 ms is acknowledged by the controller ramp compensation the ncp1253 includes an internal ramp compensation signal. this is the buffered oscillator clock delivered during the on time only. its amplitude is around 2.5 v at the maximum duty ? cycle. ramp compensation is a known means used to cure sub harmonic oscillations in ccm ? operated current ? mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ? cycle greater than 50%. to lower the current loop gain, one usually injects between 50% and 100% of the inductor downslope.
ncp1253 http://onsemi.com 14 rsense rcomp 20k 0v 2.5 v cs + ? l.e.b from fb setpoint latch reset on figure 29. inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in ccm operation in the ncp1253 controller, the oscillator ramp features a 2.5 v swing. if the clock operates at a 65 khz frequency, then the available oscillator slope corresponds to: s ramp v ramp,peak d max t sw 2.5 0.8 15 133 kv sor133mv s (eq. 6) in our flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s ratio of 1:0.25. the off ? time primary current slope s p is thus given by: s p v out v f n s n p l p ( 19 0.8 ) 4 770 103 ka s (eq. 7) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 103k 0.33 34 kv sor34mv s (eq. 8) if we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 133 mv/ s, the divider ratio ( divratio ) between r comp and the internal 20 k resistor is: divratio 17m 133m 0.127 (eq. 9) the series compensation resistor value is thus: r comp r ramp divratio 20k 0.127
2.5 k (eq. 10) a resistor of the above value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small 100 pf capacitor, from the current sense pin to the controller ground for improved noise immunity. please make sure both components are located very close to the controller.
ncp1253 http://onsemi.com 15 package dimensions ? 6 case 318g ? 02 issue u 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1253/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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